VHDL 16BIT Decoder pentru FPGA

Acest cod foloseste algoritmul "Shift Add-3"

O sa adaug mai multe comentari umpic mai tarziu, dar s-ar putea sa ajute foarte mult pe cineva


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bcd16 is
Port ( number : in STD_LOGIC_VECTOR (15 downto 0);
bcd : out STD_LOGIC_VECTOR (15 downto 0));
end bcd16;

architecture Behavioral of bcd16 is

begin

process(number)
variable z: std_logic_vector(32 downto 0);
begin

--initialize
z:=(others=>'0');

--set number
z(16 downto 1) := number;

for i in 0 to number'HIGH loop

if z(20 downto 17) > 4 then
z(20 downto 17) := z(20 downto 17) +3;
end if;

if z(24 downto 21) > 4 then
z(24 downto 21) := z(24 downto 21) +3;
end if;

if z(28 downto 25) > 4 then
z(28 downto 25) := z(28 downto 25) +3;
end if;

if z(32 downto 29) > 4 then
z(32 downto 29) := z(32 downto 29) +3;
end if;

--shift the string
z(z'HIGH downto 1) := z(z'HIGH-1 downto 0);
end loop;

bcd <= z(32 downto 17);
end process;
end Behavioral;